1. Field of Use
The present invention relates to cache memory systems and more particularly to cache memory systems utilized in multiprocessor systems.
2. Prior Art
It is well known that cache memories have been highly effective in increasing the throughput of small and large monoprocessor and multiprocessor systems. In such systems, caches are frequently configured in a so-called private cache arrangement in which the cache memory is dedicated to a single processor.
To increase system throughput, systems have increased the number of processing units, each connecting a cache memory which, in turn, connected to main memory and the other units of the overall system via an asynchronous system bus. In such systems, the independently operating processing units produce unsynchronized overlapping requests to main memory. This can substantively affect cache coherency which is the ability of the cache to accurately and correctly track the contents of main memory. The result is that processing units can be forced to operate with stale data which could eventually bring the system to a halt.
In general, there have been two basic approaches employed in maintaining cache coherency. The first termed a write through approach employs a listener device which detects the occurrence of any write operations made to main memory and updates the contents of the cache. The second approach employs circuits which invalidate the data contents of the cache locations when any other system unit writes into a main memory location which has been mapped into a processing unit's cache.
Employing the write through approach, one prior art cache system detects when any data is read or written into main memory by another unit prior to the receipt of the requested data which falls within a given address range. If it does, the cache is bypassed and the requested data is transferred to the requesting processing unit. While this ensures cache coherency, the process of bypassing cache can result in decreased system efficiency. This occurs as the system becomes busier due to the addition of more and faster processing units resulting in a substantial decrease in cache hit ratio.
Accordingly, it is a primary object of the present invention to provide a cache memory which maintains cache coherency without decreasing system efficiency.
It is a further object of the present invention to maintain a cache coherency notwithstanding unsynchronized overlapping memory requests by a number of independently operated processing units which connect to a system bus through independent interfaces.